1. The Field of the Invention
The present invention relates to methods for manufacturing semiconductor devices. More particularly, the present invention relates to a method of forming shallow trench isolation regions for a semiconductor device.
2. The Relevant Technology
Electronic devices such as field-effect transistors (FETs) are useful in fabricating integrated circuits such as those used in memory chips and microprocessors. The FETs used in high performance complementary metal oxide semiconductor (CMOS) circuits require advanced isolation techniques for filling recessed field oxide regions. One common isolation technique is known as local oxidation of silicon (LOCOS).
In the LOCOS technique, a thermal oxide liner is formed on a substrate, followed by an island of silicon nitride being formed thereover. The substrate is then placed in an oxidation steam ambient at a high temperature to oxidize the exposed silicon, with the silicon nitride forming a barrier to the steam ambient. The energetic hydrogen and oxygen ions in the steam ambient react with the exposed silicon at high temperature to form a glass which grows by consuming the silicon to form silicon dioxide.
While LOCOS is suitable for certain applications, it has some disadvantages. For example, the LOCOS process is often not suitable for deep submicron dimensions for density driven memory applications because it can result in an undesirable isolation encroachment into the active area of the device. This is commonly referred to in the industry as a "bird's beak." One of the problems of the LOCOS technique is that when a device is scaled down to smaller geometries, it is harder to control the length of the bird's beak, resulting in a very high stress in the silicon leading to stress related defects such as undesirable current leakage.
In other conventional isolation techniques such as shallow trench isolation (STI), islands of nitride are formed and then a trench etch is done to trench the silicon around the islands of nitride. This results typically in a very abrupt-shaped trench. The trenches are subsequently filled with an oxide insulator material, and then polished back and isolated out. While the use of STI leads to many desirable circuit device properties, the technique also possesses some disadvantages. One significant drawback common in STI processes is the presence of "edge conduction," which is excessive current leakage in the upper region between the top of a filled oxide trench and an adjacent silicon mesa. Devices which exhibit high edge conduction are characterized by significant parasitic leakage, which is very undesirable.
A method for forming trench-isolated FET devices to improve subthreshold leakage characteristics is disclosed in U.S. Pat. No. 5,643,822 to Furukawa et al. This method involves forming a vertical slot within a stack structure disposed on an oxide covered silicon substrate, and then forming spacers on the sidewalls of the slot. A trench is then etched in the substrate, followed by removal of the spacers to uncover a horizontal ledge on the exposed surfaces of the substrate adjacent to the trench. The ledge is then perpendicularly implanted with a suitable dopant to suppress edge conduction in the device. This method results in an abrupt-shaped trench with sharp corners which can cause undesirable electrical characteristics in the trench. The sharp corners of the trench can also lead to difficulties in depositing the trench with a filler material during subsequent processing. The sharp corners can lead to pinching off the upper opening to the trench during deposition before the trench is filled, leaving an undesirable void in the trench.
Accordingly, there is a need for an improved semiconductor trench forming method that overcomes or avoids the above problems and difficulties.